Job Title: Mixed Signal Verification Engineer
Location: Sunnyvale, California (Onsite)
Job Description:
1. Fluent in system verilog real number modeling
2. Familiarity with writing regression tests for analog behavioral model verification
3. Familiarity with generating randomized vectors for analog behavioral model verification
4. Familiar with developing checker & writing assertions.
5. Good communication skills
6. Good debug skills
7. Experienced with gate level parasitic annotated simulations.
9. Hands on experience with UVM
System Verilog real number modeling
Writing regression tests for analog behavioral model verification
Generating randomized vectors for analog behavioral model verification
Developing checker & writing assertions.
This is running mixed signal - DMS simulations and developing system verilog and EEnet based analog models
Job Type: Contract
Pay: $68.16 - $77.22 per hour
Expected hours: 40 per week
Benefits:
- 401(k)
- 401(k) matching
- Dental insurance
- Health insurance
- Vision insurance
Schedule:
- 8 hour shift
- Day shift
- Monday to Friday
Ability to Relocate:
- Sunnyvale, CA: Relocate before starting work (Required)
Work Location: On the road
