You will be responsible for understanding the digital design at system level, develop testplan for functional and circuit performance verification, testbench architecture, develop the scalable testbench using the HVLs, test case development, debugging, coverage model development, & coverage closure.
Job Requirements:
- Develop UVM testbenches from scratch.
- Develop Pre-Silicon functional validation tests to verify if the system will meet design requirements.
- Create test plans for RTL validation.
- Define and run system simulation models.
- Find and implement corrective measures for failing RTL tests and analyze and use results to modify testing.
- Coverage analysis and closure.
- Working on next generation high speed protocols and SoCs.
Qualifications:
- Minimum Bachelor’s degree in Electronics, Electrical or Computer Engineering, Math, Physics, or related fields
- Expertise in logic design verification with various tools and methodologies including System Verilog, Perl, OVM/UVM, logic simulators, and coverage tools.
- Must be a team player, with a demonstrated experience technically influencing others.
- Strong problem-solving skills.
- Excellent verbal and written communication skills.Ability to work effectively in a team as well as individually with excellent communication and interpersonal skills
- Brownie points if you have experience in
- PCIE, CXL, Ethernet, Wireless and Memory controllers.
Job Types: Full-time, Contract
Pay: $80,000.00 - $168,544.00 per year
Work Location: Remote
